1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and particularly to a semiconductor integrated circuit device having at least a test mode for externally monitoring an internal voltage. Specifically, this invention relates to a semiconductor integrated circuit device having an internal power supply voltage generating circuit for generating an internal power supply voltage according to a reference voltage, and more specifically to a configuration permitting externally monitoring or externally changing the reference voltage.
2. Description of the Background Art
Now, as an example of the semiconductor integrated circuit device, a semiconductor memory device is considered. The semiconductor memory device has been made with higher integration and higher density to obtain an increased storage capacity, and accordingly, the elements or the components of the device have been miniaturized. To ensure the reliability of these miniaturized elements such as a MOS transistor (insulated gate type field effect transistor), the operating power supply voltage should be made low. Such a lowering of the operating power supply voltage can reduce the power dissipation which is proportional to the square of the operating power supply voltage. External logics and processors, however, have not been miniaturized to the degree of the semiconductor memory device. Therefore, the power supply voltage for those devices cannot be made as low as that for the semiconductor memory device, because their high-speed operation will not be ensured. In addition, the miniaturized memory devices must retain compatibility with previous-generation semiconductor memory devices.
Therefore, the power supply voltage provided from an outside of the semiconductor memory device, such as a system power supply voltage, is down converted within the device to generate an internal power supply voltage at a required voltage level.
FIG. 19 is a diagram showing an example of the configuration of a conventional internal power supply circuit. Referring to FIG. 19, the internal power supply circuit includes a reference voltage generating circuit RFG which generates reference voltage Vref at a prescribed voltage level, and an internal voltage down converter VDC which compares reference voltage Vref from the reference voltage generating circuit RFG with the voltage on an internal power supply line IVL, and according to the result of comparison, supplies current from an external power supply node EX onto internal power supply line IVL to adjust the voltage level on the internal power supply line IVL to generate an internal power supply voltage intVcc.
The internal voltage down converter VDC includes a comparator CMP for comparing reference voltage Vref with internal power supply voltage intVcc on internal power supply line IVL, and a drive transistor DR formed of a p channel MOS transistor and for supplying current from external power supply node EX onto internal power supply line IVL according to the output signal from the comparator CMP. Comparator CMP has a positive input receiving internal power supply voltage intvcc on internal power supply line IVL and a negative input receiving reference voltage Vref.
When internal power supply voltage intvcc is higher than reference voltage Vref, the internal voltage down converter VDC pulls up the output signal from comparator CMP to a high level for rendering drive transistor DR nonconductive to stop current supply from external power supply node EX to internal power supply line IVL. On the other hand, if internal power supply voltage intvcc on internal power supply line IVL is lower than reference voltage Vref, the comparator CMP outputs a signal at a low level, increasing the conductance of drive transistor DR, and thus the current in proportion to the difference between the internal power supply voltage intVcc and the reference voltage Vref from external power supply node EX is supplied to internal power supply line IVL through drive transistor DR. As a result, the voltage level of internal power supply voltage intvcc is maintained substantially at the same level as reference voltage Vref.
FIG. 20 is a diagram showing an example of the configuration of reference voltage generating circuit RFG shown in FIG. 19, which is described, for example, in Japanese Patent Laying-Open No. 7-37381.
Referring to FIG. 20, the reference voltage generating circuit RFG includes: a p channel MOS transistor P1 connected between external power supply node EX and a node M1 and having a gate receiving a ground voltage; an n channel MOS transistor N1 connected between node M1 and a ground node and having its gate connected to node M1; a p channel MOS transistor P2 connected between external power supply node EX and a node M2 and having its gate connected to node M2; an n channel MOS transistor N2 connected between node M2 and a ground node and having its gate connected to node M1; a p channel MOS transistor P3 connected between external power supply node EX and a node M4 and having its gate connected to node M2; a p channel MOS transistor P4 connected between node M4 and node M3 and having its gate connected to node M3; and an n channel MOS transistor N3 connected between node M3 and a ground node and having its gate connected to node M1.
The two p channel MOS transistors P2 and P3 constitute a current mirror circuit, and their size ratio (size being a ratio of gate width to gate length) is set to 1:1. Meanwhile, each of the n channel MOS transistors N2 and N3 constitutes a current mirror circuit with n channel MOS transistor N1. The gate width to gate length ratio of n channel MOS transistor N2 is set to one half (xc2xd) that of n channel MOS transistor N3.
The reference voltage generating circuit RFG further includes a p channel MOS transistor P5 connected between external power supply node EX and node M3 and having its gate connected to node M3, a p channel MOS transistor P6 connected between external power supply node EX and a node M5 and having its gate connected to node M4, and diode-connected p channel MOS transistors P7, P8 and P9 connected in series to one another between node M5 and a ground node.
The absolute value of threshold voltage of p channel MOS transistor P5 is set higher than that of p channel MOS transistor P4. The ratio of gate width to gate length of p channel MOS transistor P6 is set at the same value as that of each of p channel MOS transistors P7-P9. Now, the operation of reference voltage generating circuit RFG shown in FIG. 20 will be described in brief.
P channel MOS transistor P1 having its gate connected to the ground node serves as a current source and generates a reference current, which in turn is supplied to n channel MOS transistor N1. N channel MOS transistors N1 and N2 constituting a current mirror circuit have the same size with each other, so that current flowing through n channel MOS transistor N2 is the same in amount as the current flowing through n channel MOS transistor N1. N channel MOS transistor N2 is supplied with current from p channel MOS transistor P2, and the mirror current of the current flowing through p channel MOS transistor P2 flows through p channel MOS transistor P3. As p channel MOS transistors P2 and P3 have the same size with each other, the same amount of current flows therethrough. The current i from p channel MOS transistor P3 flows through p channel MOS transistor P4 and n channel MOS transistor N3 to the ground node.
The ratio of gate width to gate length of n channel MOS transistor N3 is set twice that of n channel MOS transistor N2, and thus the current 2i, twice the magnitude of current i flowing through p channel MOS transistors P3 and P4, flows through n channel MOS transistor N3. The remaining current i is supplied from p channel MOS transistor P5 to n channel MOS transistor N3. The absolute value of threshold voltage of p channel MOS transistor P5 is set greater than that of p channel MOS transistor P4. Now, assume that the absolute value of threshold voltage of p channel MOS transistor P4 is represented by Vthp4, and the absolute value of threshold voltage of p channel MOS transistor P5 is represented by Vthp5. In this situation, as p channel MOS transistor P5 is operating in a diode mode, the voltage V(M3) of node M3 is represented by the following expression:
V(M3)=extVccxe2x88x92Vthp5.
Meanwhile, as p channel MOS transistor P4 is also operating in a diode mode, the voltage of node M4, V(M4) is expressed as follows:
V(M4)=V(M3)+Vthp4=extVccxe2x88x92(Vthp5xe2x88x92Vthp4).
Node M4 is connected to the gate of p channel MOS transistor P6, and thus p channel MOS transistor P6 supplies a constant current ir according to the constant voltage on nodes M4. Each of p channel MOS transistors P7-P9 has the same size as the p channel MOS transistor P6, and therefore each of these p channel MOS transistors P7-P9 generates the same gate-to-source voltage as p channel MOS transistor P6 does. That is, the source-to-gate voltage of p channel MOS transistor P6 is Vthp5xe2x88x92Vthp4, and each of p channel MOS transistors P7-P9 causes a voltage drop at the same voltage level as Vthp5xe2x88x92Vthp4. Therefore, the reference voltage Vref from node M5 is expressed by the following equation:
Vref=3(Vthp5xe2x88x92Vthp4).
This reference voltage Vref is determined based on the difference between the absolute values of threshold voltages of p channel MOS transistors P4 and P5, and becomes a constant voltage independent of external power supply voltage extVcc, provided that the external power supply voltage extVcc is higher than a predetermined voltage level and that all the p channel MOS transistors P7-P9 are conductive. Internal power supply voltage intVcc is set essentially at the same voltage level as reference voltage Vref. Therefore, the voltage level of internal power supply voltage intVcc, used as the operating power supply voltage for internal circuitry, attains a constant voltage level independent of the voltage level of external power supply voltage extvcc.
Reference voltage generating circuit RFG shown in FIG. 20 has reference current ir made considerably small in value in order to keep power dissipation sufficiently small. In the reference voltage generating circuit RFG configured as shown in FIG. 20, current ir supplied from p channel MOS transistor P6 flows through p channel MOS transistors P7-P9, causing a constant voltage drop at each of p channel MOS transistors P7-P9, and thus reference voltage Vref at a constant voltage level is generated. Accordingly, reference voltage generating circuit RFG shown in FIG. 20 has no current supplying capability for an external load. If current ir supplied from p channel MOS transistor P6 flows into an external load, the current value flowing through p channel MOS transistors P7-P9 will change, and the voltage level of reference voltage Vref will change consequently. Therefore, in the case a noise occurs on node M5, it will not be absorbed (because of the absence of current supply), making the configuration extremely susceptible to noise.
If noise is not absorbed, the voltage level of reference voltage Vref will vary, and accordingly the voltage level of internal power supply voltage intVcc will vary.
In the configuration of reference voltage generating circuit RFG as illustrated in FIG. 20, a resistance element can be connected between node M5 and a ground node. In this case, reference voltage Vref is determined by both reference current ir and the resistance value of the resistance element. In this case, the resistance value of the resistance element is made extremely high in order to make current consumption sufficiently small. Therefore, the configuration that utilizes the resistance element in order to generate the reference voltage also has considerably small current supplying capability, and thus has a disadvantage that it is susceptible to noise at the output node. Several tests are conducted for semiconductor memory devices. The reference voltage Vref is externally monitored in a test mode for tuning the voltage level of internal power supply voltage intVcc. Further, a test for measuring an estimation parameter (such as operating margin) of the semiconductor memory device is performed. In these test modes, the following problems arise in the conventional reference voltage generation circuit.
FIG. 21 is a diagram schematically showing an arrangement for externally monitoring the voltage level of reference voltage Vref generated by reference voltage generating circuit RFG. Referring to FIG. 21, on the semiconductor chip CH where the semiconductor memory device is formed, a pad PD is arranged in the vicinity of reference voltage generating circuit RFG. The pad PD is connected through an interconnection line SG to the output node of reference voltage generating circuit RFG. Pad PD is a test-dedicated pad, and is not connected to a lead terminal after packaging. A test probe PB from a tester TU is contacted to the pad formed on the semiconductor chip CH, and the voltage level on pad PD is monitored.
When the tester TU has a voltmeter connected to the test probe PB, reference voltage generating circuit RFG having no current supplying capability cannot sufficiently charge the path from pad PD through test probe PB to the voltmeter in tester TU, and therefore, the voltage level of reference voltage Vref cannot be measured in tester TU accurately.
There is another way of measuring the voltage level of reference voltage Vref generated from reference voltage generating circuit RFG, in which pad PD is provided with current from test probe PB using the tester TU, and the voltage level is measured dependent on whether or not current flows through the test probe PB. In this case, the current supplied from tester TU through test probe PB will be transmitted through pad PD and interconnection line SG to the output node of reference voltage generating circuit RFG. Reference voltage generating circuit RFG is essentially a voltage follower circuit with a small output impedance. Therefore, the current supplied by test probe PB flows into the output node and causes the voltage level of reference voltage Vref to change, thereby making it difficult to measure the level of reference voltage Vref accurately.
Further, this test is carried out on a semiconductor chip CH present on a wafer, with test probe PB from tester TU connected to pad PD. When testing, a jig called a test card is employed to allow test probes to contact with all the pads formed on a semiconductor chip CH. Therefore, noise from these test probes, such as a cross-talk is transmitted to pad PD, causing the voltage level of reference voltage Vref of reference voltage generating circuit RFG to change, thereby making it difficult to measure the voltage level with accuracy.
FIG. 22 is a diagram schematically showing the overall configuration of a semiconductor memory device. Referring to FIG. 22, the semiconductor memory device includes a memory cell array MA having a plurality of memory cells arranged in a matrix of rows and columns, a sense amplifier band SAB having a plurality of sense amplifier circuits provided corresponding to respective columns of memory cell array MA, to sense, amplify and latch the data of the memory cells read out on the corresponding columns when activated, a peripheral circuit PC for making an access to memory cell array MA, and a sense amplifier control circuit SAC for controlling the sense amplifier circuits in sense amplifier band SAB. The peripheral circuit PC may include a row decoder for selecting a row and an internal write/read circuit for writing/reading data. It may also include circuits for generating various control signals.
A peripheral circuit dedicated internal power supply circuit IGP is provided for peripheral circuit PC, and a sense amplifier dedicated internal power supply circuit IGS is provided for sense amplifier control circuit SAC. In the vicinity of the peripheral circuit dedicated internal power supply circuit IGP and sense amplifier dedicated internal power supply circuit IGS, pads PDP and PDS are disposed respectively. Peripheral circuit dedicated internal power supply circuit IGP and sense amplifier dedicated internal power supply circuit IGS each include both reference voltage generating circuit RFG and internal voltage down converter VDC shown in FIG. 19. However, the level of the internal power supply voltage output from peripheral circuit dedicated internal power supply circuit IGP is set slightly higher in order to permit peripheral circuit PC to operate at high speed.
The internal power supply voltage fed by sense amplifier control circuit SAC for driving sense amplifier band SAB (sense amplifier power supply voltage) is set lower than that supplied to peripheral circuit PC in order to ensure the reliability of the memory cell transistors in memory cell array MA. As a result, the internal power supply voltage output from sense amplifier dedicated internal power supply circuit IGS is set at a voltage level lower than the internal power supply voltage output from peripheral circuit dedicated internal power supply circuit IGP. In memory cell array MA, the voltage transmitted onto a selected word line is (normally 1.5 times) higher than the operating power supply voltage, and accordingly, the voltage level to be transmitted into memory cell array MA is set low in order to prevent the gate insulating film of each memory cell transistor (MOS transistor) from suffering a dielectric breakdown when the boosted voltage is applied.
As illustrated in FIG. 22, pads for monitoring the reference voltage, PDP and PDS, are arranged respectively for peripheral circuit dedicated internal power supply circuit IGP and sense amplifier dedicated internal power supply circuit IGS. These pads PDP and PDS are for use in a wafer level test, and not used after packaging. Therefore, a problem arises with respect to the semiconductor memory device that the chip area cannot be reduced because of the large area occupied by pads PDP and PDS. In addition, if the number of the required pads increases, it will become more complicated to align the pads with test probes in testing, and will consequently lower the efficiency of the testing operation.
The problem that the number of pads increases will be encountered not only where monitoring the reference voltage for generating an internal power supply voltage, but also where externally monitoring the voltage levels of internal voltages generated in the semiconductor memory device, such as a bit line precharge voltage, a cell plate voltage, a substrate bias voltage, an internal power supply voltage, and a word line driving voltage.
Moreover, the problem associated with externally monitoring an internal voltage is experienced not only in the semiconductor memory device, but also in other semiconductor integrated circuit devices including logics.
Furthermore, the problem with the pad number will also arise when the xe2x80x9cforcexe2x80x9d test is conducted for measuring the operating margin and others of an internal circuit by externally setting the level of a desired internal voltage to a desirable voltage level.
It is an object of the present invention to provide a semiconductor integrated circuit device capable of easily conducting a test on a desired internal voltage with accuracy.
It is another object of this invention to provide a semiconductor integrated circuit device capable of externally monitoring as well as externally setting the internal voltage accurately.
It is still another object of the present invention to provide a semiconductor integrated circuit device capable of easily conducting a test on a plurality of internal voltages without increasing the chip area.
It is a further object of the present invention to provide a semiconductor integrated circuit device capable of easily and accurately conducting a test on a reference voltage used for generating an internal power supply voltage without increasing the chip occupation area.
The semiconductor integrated circuit device according to an aspect of the present invention includes at least one reference voltage generating circuitry, internal power supply voltage generating circuitry for comparing a voltage corresponding to the reference voltage generated by the at least one reference voltage generating circuitry with a voltage on an internal power supply line to adjust the voltage level on the internal power supply line according to the result of comparison, a pad, and driving circuitry provided between the pad and an output of the at least one reference voltage generating circuitry for receiving the reference voltage output from the at least one reference voltage generating circuitry to generate a voltage substantially at the same level as the received reference voltage for transmission to the pad.
The semiconductor integrated circuit device according to another aspect of the invention includes a plurality of voltage transmitting lines each having an internal voltage at a predetermined voltage level transmitted thereon, a pad, and connecting circuitry provided between the pad and each of the plurality of voltage transmitting lines, and responsive to a select signal for electrically connecting the pad to a voltage transmitting line designated by the select signal.
The semiconductor integrated circuit device according to a further aspect of the invention includes a plurality of voltage transmitting lines each having an internal voltage at a predetermined voltage level transmitted thereon, a pad, connecting circuitry provided between each of the plurality of voltage transmitting lines and a first internal node, and responsive to a select signal for electrically connecting the pad to a voltage transmitting line designated by the select signal, and driving circuitry provided between the first internal node and the pad, and for receiving the voltage on the voltage transmitting line selected by the connecting circuitry to generate a voltage substantially at the same level as the received voltage for transmission to the pad.
By providing driving circuitry between the pad and the output of the reference voltage generating circuit having an extremely small current supplying capability, influence of the noise at the pad on the reference voltage generating circuit can be prevented. Also, by driving the pad by driving circuitry, the pad can be driven with a relatively large current supplying capability, and thus the level of the reference voltage can be externally monitored reliably.
Furthermore, by providing a plurality of internal voltage transmitting lines with connecting circuitry for selective connection with the pad, a test on a plurality of internal voltages can be conducted using a single pad. Accordingly, increase in the number of pads is suppressed to restrict an increase in a chip occupation area, and also the contact of the test probes of the test card with the pad will be made easier, and therefore the operation upon the testing can be simplified.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.